Digital

Wednesday, August 8, 2018

11:36 AM

#*************************************RTL Design interview questions**********************************#

1. What is the difference between reg and wire.

2. What is the difference bw latch and fllipflop?

http://www.differencebetween.net/technology/difference-between-latch-and-flip-flop/

3. What is the meaning of tri0,tri1,wand,wor.
4. Explain about project what you mention.
5. Learn spyglass.
6. Difference bw synchronous and asynchronous in synthesis perspective.
7. Difference bw setup and hold time.
8. Explain about asynchronous FIFO.
9. Clock divider ckts.
10. 3 bit NAND gate with 2 bit NAND gate .
11. Difference bw latch and flipflop.
12. Draw FSM for 011010.
13. Timing analysis i. factors.

ii. concepts

iii. setup and hold violation calculations.

14. Explain time scale units.
15. Difference bw casex and casez.
16. What is the difference bw == and ===.
17. Difference bw blocking and non-blocking.
18. What is counter.
19. Write FSM for 2’s compliment, parity checker, parity generator, JK,D,SR,T.
20. Draw AND,OR,NOR,NAND,XOR,XNOR using CMOS.
21. Draw the all shift registers ex.R,L, Universal shift registers. And also Verilog codes for all shift registers.

i.SISO

ii.SIPO

iii.PISO

iv.PIPO

22. Flip flop conversions.
23. Synchronous and asynchronous reset synthesis circuits.
24. What is difference bw initial and always block.
25. What is difference bw sequential and combinational ckts.
26. What are the Verilog event regions.
27. How synthesis if-else, case statements and for loops.
28. 2 to 4 decoder Verilog code and testbench.
29. Hex to decimal conversions.
30. One-hot muxing.
31. draw the edge triggered d latch
32. fsm sequence detection for 10110 with overlapping and non_overlapping.

digital interview questions websites
1. http://asic.co.in/Index_files/Digital_interview_questions1.htm
2. http://only-vlsi.blogspot.in/search/label/Interview%20Questions
3. http://www.vlsiinterviewquestions.org/category/digital-design/
4. http://hellovlsi.blogspot.in/
5. http://www.asic-world.com/verilog/questions.html
6. http://www.asicguru.com/verilog/interview-questions/16/
7. https://www.scribd.com/doc/38961608/Verilog-Interview-Questions-With-Answers
8. https://sites.google.com/site/interviewquestionsandanswers/verilog-interview-questions
9. https://www.quora.com/What-are-tough-interview-questions-asked-on-verilog
10. https://ideaspankaj.wordpress.com/category/system-verilog-questions/
11. http://www.verificationguide.com/p/systemc-interview-questions.html
12. http://www.testbench.in/IQ_00_INDEX.html
13. https://www.quora.com/What-are-Digital-Logic-Design-interview-questions
14. https://www.indiabix.com/digital-electronics/questions-and-answers/
15. https://asicdigitaldesign.wordpress.com/category/interview-questions/page/3/
16. https://www.wisdomjobs.com/e-university/digital-electronics-interview-questions.html
17. http://vhdlguru.blogspot.in/2010/04/here-are-some-common-interview.html
18. http://blog.digitalelectronics.co.in/2004/12/latch-vs-flip-flop.html
19. http://vlsibasic.blogspot.in/2014/10/clock-skew.html
20. http://asic-design-verification.blogspot.in/2011/03/difference-between-initial-block-and.html
21. http://vlsibuzz.blogspot.in/2009/11/what-is-difference-between-intial-and.html
22. http://sagar5258.blogspot.com/2016/04/singleton-class-in-system-verilog.html

                                                                      ASSESMENT LEVEL -1

1. What is the binary equivalent of the decimal number 368?
2. The Gray code for decimal number 6 is equivalent to
3. A ring counter consisting of five Flip-Flops will have ______ states
4. The 2’s complement of the number 1101101 is _________
5. What is the correction to be applied in binary  decimal adder to make the generated sum valid
6. (734)8=( )16
7. When simplified with Boolean Algebra (x + y)(x + z) simplifies to

8. If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops

    in cascade is

9.  A device which converts BCD to Seven Segment is called____________

10. The logic circuit given below (Fig.1)  .Identify the logic circuit.

  11. The simplification of the Boolean expression (A’BC’)’+ (AB’C)’is

  12. The simplified logic of the below logic diagram is ?  

13. The hexadecimal number for (95.5)base10 is

15. The octal equivalent of (247)base 10 is

16. The process of entering data into a ROM is called ______________

17. How many address bits are required to represent a 32 K memory

18. Shifting a register content to left by one bit position is equivalent to

19. Evaluate x = A’B+C(A.D)’using the convention A = True and B = False.

20. Design 3 input nand gate using 2X1 mux’s and inverter?

21. Design a four-input NAND gate using only two-input NAND gates.

22. Design XOR gate using just NAND gates.

23. Find The output of the combinational circuit is

24. A 4:1 multiplexer (below) is to be used for generating the output carry of a full adder. A and B are the bits to be added while Cin is the input carry and Cout is the output carry. A and B are to be used as the select bits with A being the more significant select bit.  What are the correct choices of inputs for all the four lines of the MUX.

                                           

25. Realize the following using 2:1 MUX

1. OR gate (2 input)
2. Full adder

26.  Design a DTL family two input

       a) AND gate

        b) OR gate

27.  Implement a 2X1 MUX using pass transistor logic

28. Implement AND gate using pass transistor logic  and CMOS logic .

29.  For the above question state the difference.

30. Calculate the power dissipated in the CMOS circuit where the  static current I static = 50 nano

       Amp. V dd = 5 V. and the output capacitance is 20 micro Farads . consider switching frequency as

      1Mhz.

                                                    Assessment- 1

31) Convert binary to grey for the following number  10010 . What is one application of grey code?

32)  Consider the figure given below.  IC 7408 is a TTL family AND gate IC .  For what conditions will the LED glow and what is the current flowing through the LED if the load resistance is 430Ω. Assume the threshold voltage of the diode is 0.7V

33)  Implement an inverter using two input NAND gate in different ways.

34) Reference to following figure what is the effect of grounding 1s full adder  Cin is grounded?

35. List the binary output at Q of JK flip flop shown in below figure after each  of eight clock pulses?

36. A  N bit Johnson counter has __________ number of used states

37. A register containing a 2’s complement number of 10110 what is the content of the register if it is  

   Divided by 2?

38. Implement EX-OR gate using 4 nand gates?

39. Design 32X1 mux using 8X1 mux and 4X1 mux?

40. Design 2X1 mux using Tri-state buffer

41. What are various types of state encoding techniques?

42. A settable flip-flop's normal starting state when power is first applied to a circuit is always the ________

    state.

43. Implement 3-input EX-NOR function using only two input EX-NOR gate

44. For output F to be 1 in the logic circuit shown, the input combination should be

     

45. For the logic shown in figure, the simplified Boolean expression for the output Y is

46.A 4X1 mux is used to implement a 3 input Boolean function as shown in figure.The Boolean function F(ABC) implemented is?

47. Convert the following Boolean equation into canonical sop form

  F(A,B,C)=A’+AB’C+BC’

48. Draw the state diagram of T-Flip Flop

49. Simplify the following expression

     ABC+ABC’+AB’C+A’BC+A’BC’+A’B’C’+A’B’C

50. The logic diagram shown below performs the function of a very common arithmetic building block.

     Identify the logic function.

51. Implement octal to binary encoder

52. Implement the function of T-Flip flop using following

       

         D-Flip flop with mux  and nand gate

53. We are implementing a 3-input AND gate using the following circuit:

We can replace BLOCK with number of (a) Buffers   or   (b) Inverters. The delay of buffer is Tp=2ns. Now we need to choose components such that we have proper output at F= X.Y.Z

54 IMPLEMENT Following function using only NOR gate

   F=AB+CD

55.Implement F(X,Y,Z)=∏(1,2,6,7) with 2X1multiplexer

56. (11101.01)2=(   )10

57.Design 2X1 Mux using logic gates

58.Implement Buffer using XNOR gate

    

                                                                ASSESMENT LEVEL -2

1). An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by doing some modifications for the above circuit . What is it ?

2.

3. There seems to be problem in below circuit find out that fault and try to rectify by    modifying the below circuit

4.

5. In the following figure , At point P the logic is stuck at 1 . what  is the final output expression at F

6. Design an one input and one output serial 2’s complimentary. The circuit accepts a string of bits from the input and generates the 2’s complement at the output. The circuit can be reset asynchronously to start and end the operation.

7. Draw state diagram that has to detect three consecutive coin tosses that results in heads?

8. Realize following Boolean expression with a decoder and nor gates

F1(A,B,C) =Σm(1,2,6)

                                             F2(A,B,C)=Σm(0,3,5)

9. The following circuit below is a NAND latch shown in the figure in the sequence indicated below

    X=0, y=1  ; X=0,Y=0 ; X=1,Y=1

10. Implement T and D flip flops using only 2X1 MUX.

11. What is the simplified expression for the below circuit

         

12. Design an asynchronous circuit to divide clock by 3.

13. A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each.

    The maximum possible time required for change of state will be

14. A staircase light is controlled by two switches one at the top of the stairs and another at

    the bottom of stairs Realize the circuit using AND-OR gates.

15. A 16-bit ripple carry adder is realized using 16 identical full adders (FA) . The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be _______.

16.)Build a decoder with 3 input lines but with only six output lines.if the value of the input corresponds to 6 or 7 then all output lines should be asserted  to signal error.

17) Decimal to binary encoder?

18) Find out the situation when the following circuit of MUX 2 to 1 would not work as expected and how can we eliminate the error.

 19) Draw the circuit to check a PALINDROME number of even bits

20) Can we implement 4 to 1 MUX using (a) three 2 to 1 MUX (b) only two 2 to 1 MUX and a OR gate & NOT gate?

                                                      

                  ASSESMENT LEVEL -3

21) How many 128×8 RAM chips are required to provide a memory capacity of 2048 bytes.

   (i) How many lines of address bus must be used to access 2048 bytes of memory.

  (ii)How many lines of these will be common to each chip?

  (iii) How many bits must be decoded for chip select? What is the size of decoder?

22) N number of XNOR gates is connected in series such that the N inputs (A0, A1, A2......)   are given in the following way: A0 & A1 to first XNOR gate and A2 & O/P of First XNOR to second XNOR gate and so on..... Nth XNOR gates output is final output. How does this circuit work? Explain in detail?

23). Design a sequence detector circuit for detecting 2 sequences 010  and 110 in a single state diagram.

:

24). Below is a circuit diagram which satisfies the state diagram on the right when Q1 is connected to A input. If we replace the XOR gate with the XNOR gate what are the modifications to be done for the same circuit so that the same state diagram is preserved.

          

25). The ripple counter shown in the given figure works as a mod_______________ counter

   

26). Design a logic which mimics a infinite width register. It takes input serially 1 bit

      at a time. Output is asserted high when this register holds a value which

      is divisible by 3 

For example: 

Input	Sequence	Value	Output
0	0	0	1
1	01	1	0
1	011	3	1

27. Design a black box whose input clock and output relationship as shown

       in diagram.

                __    __    __    __    __    __    __    __    __  

clk     __|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__

           __          __          __          __          __  

Output  __|  |________|  |________|  |________|  |________|  |__

9. A four-channel scope is used to check the counter in the figure given below.

Are the displayed waveforms correct?.

10. Design an adder /subtractor circuit with one selection variable s and two inputs A and         

     B. (With min number of gates)

  

     When s=0 the circuit performs A+B.

     When s=1 the circuit performs A-B by taking the 2’s complement

11. Consider the following expression only using half adder?

D=AB’C+A’BC

E=ABC’+A’C+B’C

12.implement 3 input EX-Nor gate using only 2 input EX-Nor gate

13.How can you convert JK flip flop to d flip flop

14.Implement 4X1 mux using decoder and or gate

15.How to make full adder circuit to work as full substractor?

16.construct a 4X16 line decoder with two 3X8 decoder Hint:it consists enable as input

17.implement a Full subtractor combinational circuit using 3 to 8 decoder and nor gate

     18. The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ( input). The counter corresponding to this circuit (all J and K inputs are 1 and 1 ) is

19. You have been hired by a group to count the number of students in the classroom.  Since the room is small, there can be only maximum of 26 students in that room. Design a circuit to keep track of the number of the people in class room. The output of the circuit tells how many students are there in the class room , also it indicates you when the class room is full.

20. A finite state machine shown below has one input, X, and one output, Z, and two state variables, A and B, and a clock input.

a) Obtain state transition table

b) Draw the state diagram.

21) The sequential circuit below has one D flip-flop, two inputs (X and Y), and one output (S). The circuit consists of a full adder circuit whose carry output is connected to a D flipflop.

a).Derive the truth table for the above circuit.

b). Draw the state diagram for this circuit (be sure to show the output S in the diagram).

c). Is the finite state machine of the Moore type or the Mealy type? Explain.

d). Assume that the timing characteristics for the flip-flop are tp = tsetup = thold = 2 µs, and for the full adder tp = 4 µs. Assuming that all inputs (X and Y) are synchronous with the system clock, what is the greatest clock speed at which the system could run

22) At Back Bay garage, Don and Larry are thinking of using an automated parking ticket machine to control the number of guest cars that a member can bring. The card reader X S Y Full adder Z C CLK D Q S tells the controller whether the car is a member or a guest car. Only one guest car is allowed per member at a discount rate only when s/he follows out the member at the exit (within the allotted time). The second guest must pay the regular parking fees. You have been hired to implement the control system for the machine which is located at the exit. Using your expertise on FSMs, design the control system.

• Signals from the card reader: MEMBER and GUEST

• Signals from the toll booth: TOKEN (meaning one toke received),

• EXP (time for discounted guest payment has expired).

• Signal to the gate: OPEN. Fee: Members are free, Guest w a Member is 1 Token, Regular Guest is 2 Tokens.

a) Draw a truth table that corresponds to the FSM.

b) Draw the equivalent Karnaugh map.

c). Turn in your state diagram, carefully labeled. Be sure to indicate which state the FSM is in after a RESET.

d). Is this a Moore or Mealy machine?