Interview_questions

#*********************************RTL Design interview questions****************************#

1. What is the difference between reg and wire.

2. What is the difference bw latch and fllipflop?

http://www.differencebetween.net/technology/difference-between-latch-and-flip-flop/

3. What is the meaning of tri0,tri1,wand,wor.
4. Explain about project what you mention.
5. Learn spyglass.
6. Difference bw synchronous and asynchronous in synthesis perspective.
7. Difference bw setup and hold time.
8. Explain about asynchronous FIFO.
9. Clock divider ckts.
10. 3 bit NAND gate with 2 bit NAND gate .
11. Difference bw latch and flipflop.
12. Draw FSM for 011010.
13. Timing analysis i. factors.

ii. concepts

iii. setup and hold violation calculations.

14. Explain time scale units.
15. Difference bw casex and casez.
16. What is the difference bw == and ===.
17. Difference bw blocking and non-blocking.
18. What is counter.
19. Write FSM for 2’s compliment, parity checker, parity generator, JK,D,SR,T.
20. Draw AND,OR,NOR,NAND,XOR,XNOR using CMOS.
21. Draw the all shift registers ex.R,L, Universal shift registers. And also Verilog codes for all shift registers.

i.SISO

ii.SIPO

iii.PISO

iv.PIPO

22. Flip flop conversions.
23. Synchronous and asynchronous reset synthesis circuits.
24. What is difference bw initial and always block.
25. What is difference bw sequential and combinational ckts.
26. What are the Verilog event regions.
27. How synthesis if-else, case statements and for loops.
28. 2 to 4 decoder Verilog code and testbench.
29. Hex to decimal conversions.
30. One-hot muxing.
31. draw the edge triggered d latch
32. fsm sequence detection for 10110 with overlapping and non_overlapping.